1. Field of the Invention
This invention relates to a process for forming an oxide layer over a stepped surface of a semiconductor wafer. More particularly, this invention relates to a two step process for forming an oxide layer over a stepped surface of a semiconductor wafer which inhibits the formations of voids in the regions being filled with oxide between raised portions of the wafer surface.
2. Description of the Related Art
The formation of oxide layers over stepped surfaces of a semiconductor wafer is a well known technique either for forming an insulating layer or a planarizing layer or both. For example, if the stepped surface is the result of the formation of raised conductive lines on the surface of the wafer over other previously formed integrated circuit structures, deposition of an oxide layer over and in between the conductive lines will serve as both insulation for the conductive lines as well as a planarizing media.
Similarly, if the stepped surface is the result of the formation of slots or trenches in the wafer, for example, to provide electrical isolation between adjacent active devices formed in the wafer, it will be desirable to at least partially fill the slot or trench with an oxide insulation material which will also serve as a planarizing material.
In both instances, a problem of void formation can occur, during the deposition of oxide, in the regions between closely spaced apart raised lines and/or in high aspect ratio trenches. Void formation occurs when oxide forms at a slower rate adjacent the bottom portions of the trench or space between raised lines than along the upper regions of the sidewalls, especially at the upper corners, which results in a necking in of the oxide and trapping of an unfilled or void region below the necked in region. Subsequent planarization may remove enough overlying oxide to expose this void region with deleterious consequences.
The use of a doped glass, which will flow when heated to a temperature below that which will damage the wafer and integrated circuit structures already constructed therein, is known to at least partially solve the problem of formation of such voids, as well as to assist in planarization of a stepped structure.
However, it is not always desirable to use doped insulation materials because of the possible migration of the dopants into the adjacent structure in the semiconductor wafer during subsequent heating as well as the hygroscopic nature of such materials.
In our parent application Ser. No. 143,800, cross-reference to which is hereby made, we taught the use of a two step chemical vapor deposition (CVD formation) of a boron phosphorus silicate glass (BPSG), using tetraethylorthosilicate (TEOS) as the source of silicon. In the process claimed therein, the first step is carried out without the assistance of a plasma to form a majority of the desired doped oxide glass under conditions which inhibit void formation, and then the balance of the deposition is carried out, in a second step, in the presence of a plasma which results in a second coating layer which is less hygroscopic.
It would, however, be desirable to be able to provide a process for forming an oxide layer over a stepped surface of a semiconductor wafer, while inhibiting void formation, which could be used to form either a doped or undoped oxide glass layer.